Tuesday, August 14, 2012

Intel Server CPU generations

Intel Xeon 5400 = Harpertown
    » Penryn microarchitecture
    » Intel 64
    » 0.045 micron (45 nm)
    » Up to 4 cores
    » Up to 3.33 GHz
    » Up to 2x6 MB L2 cache
    » MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1
    » Demand-Based Switching except E5405, L5408
    » Enhanced Intel SpeedStep Technology (EIST) - except E5405
    » XD bit (an NX bit implementation)
    » HyperThreading
    » Virtualization (Intel VT-x, Intel VT-d)

Intel Xeon 5500 = Nehalem-EP
    » Nehalem microarchitecture
    » Intel 64
    » 0.045 micron (45 nm)
    » Up to 4 cores
    » Up to 3.33 GHz
    » Up to 8 MB L3 cache
    » MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2
    » Enhanced Intel SpeedStep Technology (EIST)
    » XD bit (an NX bit implementation)
    » HyperThreading
    » Virtualization (Intel VT-x, Intel VT-d)
  
Intel Xeon 5600 = Westmere-EP
    » Nehalem microarchitecture
    » Intel 64
    » 0.032 micron (32 nm)
    » Up to 6 cores
    » Up to 4.4 GHz
    » Up to 12 MB L3 cache
    » MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2,
    » Enhanced Intel SpeedStep Technology (EIST)  
    » XD bit (an NX bit implementation)
    » TXT
    » AES-NI
    » Smart Cache
    » Demand-Based Switching
    » HyperThreading
    » Virtualization (Intel VT-x, Intel VT-d)
    » Turbo Boost (except E5603, E5606, E5607, L5609)

Intel Xeon E5-2600 = Sandy Bridge-EP   
    » Sandy Bridge microarchitecture
    » Intel 64
    » 0.032 micron (32 nm)
    » Up to 8 cores
    » Up to 3.3 GHz
    » Up to 20 MB L3 cache
    » MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX
    » Enhanced Intel SpeedStep Technology (EIST)
    » XD bit (an NX bit implementation)
    » TXT
    » AES-NI
    » Smart Cache
    » Demand-Based Switching
    » HyperThreading
    » Virtualization (Intel VT-x, Intel VT-d)
    » Turbo Boost (except E5-2603, E5-2609)

Caution: Information was collected from various public sources therefore the completeness and correctness is not guaranteed.

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